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mb96f6a5r/a mb96f6a6r f 2 mc - 16fx mb966a0 series 16 - bit proprietary microcontroller datasheet cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 04715 rev.*a revised may 25, 2016 mb966a0 series is based on cypress s advanced f 2 mc - 16fx architecture (16 - bit with instruction pipeline for risc - like performance). the cpu uses the same instruction set as the established f2mc - 16lx family thus allowing for easy migration of f 2 mc - 16lx software to the new f 2 mc - 16fx products. f 2 mc - 16fx product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, red uced power consumption and faster start - up time. for high processing speed at optimized power consumption an internal pll can be selected to supply the cpu with up to 32mhz operation frequency from an external 4mhz to 8mhz resonator. the result is a minimu m instruction cycle time of 31.2ns going together with excellent emi behavior. the emitted power is minimized by the on - chip voltage regulator that reduces the internal cpu voltage. a flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the cpu speed. f eatures technology 0.18 ? m cmos cpu ? f 2 mc - 16fx cpu ? optimized instruction set for controller applications (bit, byte, word and long - word data types, 23 different addressing modes, barrel shif t, variety of pointers) ? 8 - byte instruction queue ? signed multiply (16 - bit ? 16 - bit) and divide (32 - bit/16 - bit) instructions available system clock ? on - chip pll clock multiplier ( ? 1 to ? 8, ? 1 when pll stop) ? 4mhz to 8 mhz crystal oscillator (maximum frequency when using ceramic resonator depends on q - factor) ? up to 8 mhz external clock for devices with fast clock input feature ? 32 .768 khz subsystem quartz clock ? 100khz/2mhz internal rc clock for quick and safe startup, clock stop detection function , watchdog ? clock source selectable from mainclock oscillator , subclock oscillator and on - chip rc oscillator, independently for cpu and 2 clock domains of peripherals ? the subclock oscillator is enabled by the boot rom program controlled by a configuration marker after a power or external reset ? low power consumption - 13 operating modes (different run, sleep, timer, stop mode s ) on - chip voltage regulator internal voltage regulator supports a wide mcu supply voltage range (min=2.7v), offering low power consumption low vol tage detection function reset is generated when supply voltage falls below programmable reference voltage code security protects flash memory content from unintended read - out dma automatic transfer function independent of cpu, can be assigned freely to res ources interrupts ? fast interrupt processing ? 8 programmable priority levels ? non - maskable interrupt (nmi) can ? supports can protocol version 2.0 part a and b ? iso16845 certified ? bit rates up to 1m bps ? 32 message objects ? each message object has its own identifier mask ? programmable fifo mode (concatenation of message objects) ? maskable interrupt ? disabled automatic retransmission mode for time triggered can applications
document number: 002 - 04715 rev.*a page 2 of 75 mb966a0 series ? programmable loop - back mode for self - test operation usart ? full duplex usarts (sci/lin) ? w ide range of baud rate settings using a dedicated reload timer ? special synchronous options for adapting to different synchronous serial protocols ? lin functionality working either as master or slave lin device ? extended support for lin - protocol to reduce int errupt load i 2 c ? up to 400 k b p s ? master and slave functionality, 7 - bit and 10 - bit addressing a/d converter ? sar - type ? 8/ 10 - bit resolution ? signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation b y software, external trigger , reload timers and ppgs ? range comparator function ? scan disable function ? adc pulse detection function source clock timers three independent clock timers (23 - bit rc clock timer, 23 - bit main clock timer, 17 - bit sub clock timer) hardware watchdog timer ? hardware watchdog timer is active after reset ? window function of watchdog timer is used to select the lower window limit of the watchdog interval reload timers ? 16 - bit wide ? prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency ? even t count function free - running timers ? signals an interrupt on overflow , supports timer clear upon match with output compare (0, 4) ? prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 , 1/2 8 of peripheral clock frequency input capture units ? 16 - bit wide ? signals an interrupt upon external event ? rising edge, falling edge or both (rising & falling) edges sensitive output c ompare units ? 16 - bit wide ? signals an interrupt when a match with free - running timer occurs ? a pair of compare registers can be used to gene rate an output signal programmable pulse generator ? 16 - bit down counter, cycle and duty setting registers ? can be used as 2 ? 8 - bit ppg ? interrupt at trigger, counter borrow and/or duty match ? pwm operation and one - shot operation ? internal prescaler allows 1, 1 /4, 1/16, 1/64 of peripheral clock as counter clock or of selected reload timer underflow as clock input ? can be triggered by software or reload timer ? can trigger adc conversion ? timing point capture ? start delay stepp ing motor controller ? stepp ing motor controller with integrated high current output drivers ? four high current outputs for each channel ? two synchronized 8/10 - bit pwms per channel ? internal prescaling for pwm clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock ? dedicated pow er supply for high current output drivers lcd controller ? lcd controller with up to 4 com ? 44 seg ? internal or external voltage generation ? duty cycle: selectable from options: 1/2, 1/3 and 1/4 ? fixed 1/3 bias ? programmable frame period ? clock source selectable from four options ( main clock, peripheral clock, subclock or rc oscillator clock) ? i nternal divider resistors or external divider resistors ? on - chip data memory for display ? lcd display can be operated in timer mode ? blank display: sele ctable
document number: 002 - 04715 rev.*a page 3 of 75 mb966a0 series ? all seg , com and v pins can be switched between general and specialized purposes sound gene rator ? 8 - bit pwm signal is mixed with tone frequency from 16 - bit reload counter ? pwm clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock real time clock ? operational on main oscillation (4mhz), sub oscillation (32khz) or rc oscillation (100khz/2mhz) ? capable to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) ? read/write accessible second/minute/hour registers ? can s ignal interrupts every half second/second/minute/hour/day ? internal clock divider and prescaler provide exact 1s clock external interrupts ? edge or l evel sensitive ? interrupt mask bit per channel ? each available can channel rx has an external interrupt for wake - up ? selected usart channels sin have an external interrupt for wake - up non maskable interrupt ? disabled after reset, can be enabled by boot - rom depending on rom configuration block ? once enabled, cannot be disabled other than by reset ? h igh or low level sensitive ? pin shared with external interrupt 0 i/o ports ? most of the external pins can be used as general purpose i/o ? all push - pull outputs (except when used as i 2 c sda/scl line) ? bit - wise programmable as input/output or peripheral signal ? bit - wise programma ble input enable ? one input level per gpio - pin (either automotive or cmos hysteresis) ? bit - wise programmable pull - up resistor built - in on chip debugger (ocd) ? one - wire debug tool interface ? break function ? hardware break: 6 points (shared with code event) ? softw are break: 4096 points ? event function ? code event: 6 points (shared with hardware break) ? data event: 6 points ? event sequencer: 2 levels + reset ? execution time measurement function ? trace function: 42 branches ? security function flash memory ? dual operation flash allowing reading of one flash bank while programming or erasing the other bank ? command sequencer for automatic execution of programming algorithm and for supporting dma for programming of the flash memory ? supports automatic programming, embedded algo rithm ? write/erase/erase - suspend/resume commands ? a flag indicating completion of the automatic algorithm ? erase can be performed on each sector individually ? sector protection ? flash security feature to protect the content of the flash ? low voltage detection du ring flash erase or write
document number: 002 - 04715 rev.*a page 4 of 75 mb966a0 series contents 1. product lineup ................................ ................................ ................................ ................................ ................................ .. 5 2. block diagram ................................ ................................ ................................ ................................ ................................ ... 6 3. pin assignment ................................ ................................ ................................ ................................ ................................ . 7 4. pin description ................................ ................................ ................................ ................................ ................................ .. 8 5. pin circuit type ................................ ................................ ................................ ................................ ............................... 10 6. i/o circuit type ................................ ................................ ................................ ................................ ................................ 14 7. memory map ................................ ................................ ................................ ................................ ................................ .... 21 8. ramstart addresses ................................ ................................ ................................ ................................ ....................... 22 9. user rom memory map for flash devices ................................ ................................ ................................ ................... 23 10. serial programming communication interface ................................ ................................ ................................ ............ 24 11. interrupt vector table ................................ ................................ ................................ ................................ ..................... 25 12. handling precautions ................................ ................................ ................................ ................................ ..................... 29 12.1 precautions for product design ................................ ................................ ................................ ................................ ... 29 12.2 precautions for package mounting ................................ ................................ ................................ .............................. 30 12.3 precautions for use environment ................................ ................................ ................................ ................................ 31 13. handling devices ................................ ................................ ................................ ................................ ...................... 32 14. electrical characteristics ................................ ................................ ................................ ................................ ............... 36 14.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 36 14.2 recommended operating conditions ................................ ................................ ................................ .......................... 39 14.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 40 14.3.1 current rating ................................ ................................ ................................ ................................ .............................. 40 14.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 43 14.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 46 14.4.1 main clock input characteristics ................................ ................................ ................................ ................................ .. 46 14.4.2 sub clock input characteristics ................................ ................................ ................................ ................................ ... 47 14.4.3 built - in rc oscillation characteristics ................................ ................................ ................................ .......................... 48 14.4.4 internal clock timing ................................ ................................ ................................ ................................ ................... 48 14.4.5 operating conditions of pl l ................................ ................................ ................................ ................................ ........ 49 14.4.6 reset input ................................ ................................ ................................ ................................ ................................ ... 49 14.4.7 power - on reset timing ................................ ................................ ................................ ................................ ................ 50 14.4.8 usart timing ................................ ................................ ................................ ................................ ............................. 51 14.4.9 external input timing ................................ ................................ ................................ ................................ ................... 53 14.4.10 i 2 c timing ................................ ................................ ................................ ................................ ................................ . 54 14.5 a/d converter ................................ ................................ ................................ ................................ .............................. 55 14.5.1 electrical characteristics for the a/d converter ................................ ................................ ................................ ........... 55 14.5.2 accuracy and setting of the a/d converter sampling time ................................ ................................ ......................... 56 14.5.3 definition of a/d converter terms ................................ ................................ ................................ ............................... 57 14.6 high current output slew rate ................................ ................................ ................................ ................................ ... 59 14.7 low voltage detection function characteristics ................................ ................................ ................................ ......... 60 14.8 flash memory write/erase characteristics ................................ ................................ ................................ ................. 62 15. example characteristics ................................ ................................ ................................ ................................ ................ 63 16. ordering information ................................ ................................ ................................ ................................ ...................... 66 17. package dimension ................................ ................................ ................................ ................................ ........................ 67 18. major changes ................................ ................................ ................................ ................................ ................................ 68 document history ................................ ................................ ................................ ................................ ................................ . 74
document number: 002 - 04715 rev.*a page 5 of 75 mb966a0 series 1. product lineup features mb96 6a0 remark product type flash memory product subclock subclock can be set by software dual operation flash memory ram - 128.5kb + 32kb 8kb mb96f6 a 5 r, mb96f6a5a product options r: mcu with can a: mcu without can 256.5kb + 32kb 16kb mb96f6 a 6 r package lqfp - 120 fpt - 120 p - m2 1 dma 4 ch usart 5 ch lin - usart 0 to 2 / 4/5 with automatic lin - header transmission/reception 2ch lin - usart 0 /1 with 16 byte rx - and tx - fifo i 2 c 1ch i 2 c 0 8/10 - bit a/d converter 3 2ch an 0 to 31 with data buffer no with range comparator yes with scan disable yes with adc pulse detection yes 16 - bit reload timer (rlt) 5 ch rlt 0 to 3 /6 16 - bit free - running timer (frt) 2ch frt 0/1 16 - bit input capture unit (icu) 8 ch ( 5 channels for lin - usart) icu 0 to 7 ( icu 0/1 /4 to 6 for lin - usart ) 16 - bit output compare unit (ocu) 4ch ocu 0 to 3 8/16 - bit programmable pulse generator (ppg) 12 ch (16 - bit) / 24 ch (8 - bit) ppg 0 to 7/12 to 15 with timing point capture yes with start delay yes with ramp no can interface 1ch can 0 32 message buffers stepping motor controller (smc) 5 ch smc 0 to 4 external interrupts (int) 16 ch int 0 to 15 non - maskable interrupt (nmi) 1ch sound generator (sg) 2 ch sg 0 /1 lcd controller 4com 44 seg com 0 to 3 seg 0 to 4 / 7 to 45 real time clock (rtc) 1ch i/o ports 95 (dual clock mode) 97 (single clock mode) clock calibration unit (cal) 1ch clock output function 2ch low voltage detection function yes low v oltage d etection f unction can be disabled by software hardware watchdog timer yes on - chip rc - oscillator yes on - chip debugger yes note: all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the g eneral i/o port according to your function use.
document number: 002 - 04715 rev.*a page 6 of 75 mb966a0 series 2. block diagram md interru p t controller dm a contro ll er peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) i 2 c 1ch i/o tim e r 1 f r t1 icu 4/5/6/7 i/o tim e r 0 f r t0 icu 0/1/2/3 ocu 0 /1/2/3 16-bit reload timer 0/1/2/3/6 5ch 8/10-bit adc 32ch can interface 1ch usart 5ch pp g 12ch (16-bit ) / 24ch (8-b i t) real t ime cloc k external interru p t stepping motor controller 5ch vcc vss pp g 0 t o p p g 7 , pp g 12 t o p p g 1 5 c peripheral bus bridg e peripheral bus bridg e 16 fx c o r e b u s ( cl kb ) tx0 rx0 sound gen e rator 2ch s go 0 , s go 1 , s g o 0_r , s g o 1 _ r s g a 0 , s g a 1 , s g a 0_r , s g a 1 _ r sin0 to sin2, s i n4, sin5, sin5 _ r s c k 0 t o s c k 2 , s c k 4 , s c k 5 , s c k 5_r sot0 t o sot2, sot4, s o t 5, sot5_r s d a 0 scl0 an0 to an31 adt g tin1_r, tin2 _r tin0 to tin3 t o t1_r, t o t2 _ r t o t 0 t o t o t 3 frck0 frck1 in6, in7 in4_r to i n 7_ r int0 to i nt15 int1_r t o in t 7 _ r l c d c on t rolle r/ d r iver 4com 44seg v0 to v3 com0 to com 3 se g 0 to s e g 4 w o t, w o t _ r dvss t t g 0 t o t t g7, t t g1 2 to t t g15 ppg0_r to p p g5_r ppg0_b to ppg7_b, ppg1 2 _b to ppg15_ b dvcc pwm1m0 to pwm1m4 pwm1p0 to pwm1p4 pwm2m0 to pwm2m4 pwm2p0 to pwm2p4 in0, in1 ou t 0_r to o u t 3_r o u t 0 t o o u t 3 frck0_r in0_r to i n 3_ r se g 7 to s e g 4 5 ck ot x 0 , ck o t x1 , ck ot x1_ r cko t 0, c k ot 0 _r, ckot1, c k ot1 _ r cpu mode cont r oller clock & boot rom m a r watchdog v ol t age regulator 16fx f l a s h m e m o r y a nmi x0 , x1 x0a, x1a rstx oc d debu g i / f avrl avrh a vss a vcc 16ch
document number: 002 - 04715 rev.*a page 7 of 75 mb966a0 series 3. pin assignment (top view) ( fpt - 120p - m21 ) *1: cmos input level only *2: cmos input level only for i 2 c *3: please set rom configuration block (rcb) to use the subclock. other than those above, general - purpose pins have only automotive input level. lqf p - 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 v s s p0 0 _3 / s e g 15 / in t 6_ r p0 0 _4 / s e g 16 / in t 7_r p0 0 _5 / s e g 17 / in6 / t t g 2 / t t g 6 p0 0 _6 / s e g 18 / in7 / t t g 3 / t t g 7 p 0 0 _7 / s e g 19 / s go 0 / i n t 14 p0 1 _0 / s e g 20 / s g a0 p0 1 _1 / s e g 21 / ck o t 1 / o u t 0 p0 1 _2 / s e g 22 / ck o t x 1 / o u t 1 / in t 15 p 0 1 _3 / s e g 23 / p p g 5 p0 1 _4 / s e g 24 / si n 4 / i n t 8 * 1 p0 1 _5 / s e g 25 / s o t 4 p0 1 _6 / s e g 26 / s c k4 / t t g 12 * 1 p0 1 _7 / s e g 27 / ck o t x 1_r / in t 9 / t t g 13 p0 2 _0 / s e g 28 / ck o t 1 _ r / in t 10 / t t g 14 p0 2 _1 / s e g 29 / in 6 _ r / tt g 15 p0 2 _2 / s e g 30 / i n 7 _ r / c k o t 0_r / i n t 12 p0 2 _3 / s e g 31 / s go 0 _ r / pp g 12 _ b p0 2 _4 / s e g 32 / s g a0_r / pp g 13 _ b p0 2 _5 / s e g 33 / o u t 0_r / in t 13 / s i n5_ r * 1 p0 2 _6 / s e g 34 / o u t 1_r p 0 2 _7 / s e g 35 / p p g 5_ r p0 3 _0 / v0 / s e g 3 6 / pp g 4_b p0 3 _1 / v1 / s e g 3 7 / pp g 5_b p0 3 _2 / v2 / s e g 3 8 / pp g 14 _ b / s o t 5_r p0 3 _3 / v3 / s e g 3 9 / pp g 15 _ b / sc k 5_ r * 1 p0 3 _4 / r x 0 / i n t 4 * 1 p 0 3 _5 / t x 0 p0 3 _6 / i n t 0 / nm i v c c v cc p1 0 _3 / p w m2m4/ p p g 7 / an31 p1 0 _2 / p w m2p4/ s c k2 / pp g 6 / an 3 0 * 1 p1 0 _1 / p w m1m4 / s o t 2 / t o t 3 / an29 p1 0 _0 / p w m1p4 / s i n2 / t i n3 / in t 1 1 / a n 2 8 * 1 p0 9 _7 / p w m2m3 / p p g 1 5 d v s s d v c c p0 9 _6 / p w m2p3 / p p g 1 4 p0 9 _5 / p w m1m3 / p p g 1 3 p0 9 _4 / p w m1p3 / p p g 1 2 p0 9 _3 / p w m2m2 / an2 7 p0 9 _2 / p w m2p2 / an 26 p0 9 _1 / p w m1m2/ a n 25 p0 9 _0 / p w m1p2 / an 24 p0 8 _7 / p w m2m1 / an2 3 / pp g 7 _b p0 8 _6 / p w m2p1 / an 2 2 / pp g 6 _b p0 8 _5 / p w m1m1 / an2 1 d v s s d v c c p0 8 _4 / p w m1p1 / an 20 p0 8 _3 / p w m2m0 / an1 9 p0 8 _2 / p w m2p0 / an 18 p0 8 _1 / p w m1m0 / an1 7 p0 8 _0 / p w m1p0 / an 16 p 0 5 _7 / a n 15 / t o t 2 / s g a 1_r p0 5 _6 / a n 14 / t i n2 / s go 1_r p0 5 _5 / a n 13 p0 5 _4 / a n 12 / i n t 2_r / w o t _ r v ss v cc p0 0 _2 / s e g 1 4 / int5 _ r p0 0 _1 / s e g 13 / in t 4 _ r p0 0 _0 / s e g 12 / in t 3 _ r p1 2 _7 / s e g 1 1 / i n t 1_r p1 2 _6 / s e g 10 / t o t 2_r / pp g 3 _b p1 2 _5 / s e g 9 / tin 2 _r / p p g 2 _ b p1 2 _4 / s e g 8 / o ut 3 _r p1 2 _3 / s e g 7 / o ut 2 _r p1 2 _2 / t o t 1 _r / p p g 1 _b p1 2 _1 / t i n 1 _r / p p g 0 _ b p1 2 _0 / s e g 4 / i n 1_r p 1 1 _ 7 / se g 3 / i n 0_r p 1 1 _ 6 / se g 2 / f r c k 0 _ r p 1 1 _ 5 / se g 1 / pp g 4 _r p 1 1 _ 4 / se g 0 / pp g 3 _r p 1 1 _ 3 / c o m3 / p p g 2_ r p 1 1 _ 2 / c o m2 / p p g 1_ r p 1 1 _ 1 / c o m1 / p p g 0_ r p 1 1 _ 0 / c o m0 rs tx p0 4 _1 / x 1 a * 3 p0 4 _0 / x 0 a * 3 v ss x 1 x 0 md p1 7 _0 debu g i/ f v ss 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 1 10 11 1 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 12 0 v ss c p0 3 _7 / int1 / si n 1 / se g 40 * 1 p1 3 _0 / int2 / s o t1 / se g 41 p1 3 _1 / int3 / s c k1 / s e g 42 * 1 p 1 3 _2 / p p g 0 / ti n0 / f r c k 1 / s e g 43 p1 3 _3 / p p g 1 / t o t0 / w o t / se g 44 p1 3 _4 / si n 0 / in t 6 / se g 45 * 1 p1 3 _5 / s o t0 / adt g / i n t7 p1 3 _6 / s c k0 / ck o t x0 * 1 p1 3 _7 / p p g 2 / c k o t 0 p0 4 _4 / p p g 3 / s d a0 * 2 p0 4 _5 / p p g 4 / sc l 0 * 2 p0 6 _0 / a n 0 / in2 _ r / sc k 5 * 1 p0 6 _1 / a n 1 / in3 _ r / s o t 5 p0 6 _2 / a n 2 / int5 / si n 5 * 1 p0 6 _3 / a n 3 / f r c k 0 p0 6 _4 / a n 4 / in0 / tt g 0 / tt g 4 p0 6 _5 / a n 5 / in1 / tt g 1 / tt g 5 p0 6 _6 / a n 6 / t i n 1 / i n 4_ r p0 6 _7 / a n 7 / t o t 1 / i n 5_ r a v c c a v rh a v r l a v s s p0 5 _0 / a n 8 p0 5 _1 / a n 9 p 0 5 _2 / a n 10 / o u t 2 / s g o 1 p0 5 _3 / a n 1 1 / o u t 3 / s g a1 v cc 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1
document number: 002 - 04715 rev.*a page 8 of 75 mb966a0 series 4. pin description pin name feature description adtg adc a/d converter trigger input pin ann adc a/d converter channel n input pin avcc supply analog circuits power supply pin avrh adc a/d converter high reference voltage input pin avrl adc a/d converter low reference voltage input pin avss supply analog circuits power supply pin c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output pin ckotn_r clock output function relocated clock output function n output pin ckotxn clock output function clock output function n inverted output pin ckotxn_r clock output function relocated clock output function n inverted output pin comn lcd lcd common driver pin debug i/f ocd on chip debugger input/output pin dvcc supply smc pins power supply dvss supply smc pins power supply frckn free - running timer free - running timer n input pin frckn_r free - running timer relocated free - running timer n input pin inn icu input capture unit n input pin inn_r icu relocated input capture unit n input pin intn external interrupt external interrupt n input pin intn_r external interrupt relocated external interrupt n input pin md core input pin for specifying the operating mode nmi external interrupt non - maskable interrupt input pin outn ocu output compare unit n waveform output pin outn_r ocu relocated output compare unit n waveform output pin pnn_m gpio general purpose i/o pin ppgn ppg programmable pulse generator n output pin (16bit/8bit) ppgn_r ppg relocated programmable pulse generator n output pin (16bit/8bit) ppgn_b ppg programmable pulse generator n output pin (16bit/8bit) pwmn smc smc pwm high current output pin rstx core reset input pin rxn can can interface n rx input pin sckn usart usart n serial clock input/output pin sckn_r usart relocated usart n serial clock input/output pin scln i 2 c i 2 c interface n clock i/o input/output pin sdan i 2 c i 2 c interface n serial data i/o input/output pin segn lcd lcd segment driver pin sgan sound generator sound generator amplitude output pin sgan_r sound generator relocated sound generator amplitude output pin sgon sound generator sound generator sound/tone output pin
document number: 002 - 04715 rev.*a page 9 of 75 mb966a0 series pin name feature description sgon_r sound generator relocated sound generator sound/tone output pin sinn usart usart n serial data input pin sinn_r usart relocated usart n serial data input pin sotn usart usart n serial data output pin sotn_r usart relocated usart n serial data output pin tinn reload timer reload timer n event input pin tinn_r reload timer relocated reload timer n event input pin totn reload timer reload timer n output pin totn_r reload timer relocated reload timer n output pin ttgn ppg programmable pulse generator n trigger input pin txn can can interface n tx output pin vn lcd lcd voltage reference pin vcc supply power supply pin vss supply power supply pin wot rtc real time clock output pin wot_r rtc relocated real time clock output pin x0 clock oscillator input pin x0a clock subclock oscillator input pin x1 clock oscillator output pin x1a clock subclock oscillator output pin
document number: 002 - 04715 rev.*a page 10 of 75 mb966a0 series 5. pin circuit type pin no. i/o circuit type * pin name 1 supply vss 2 f c 3 p p03_7 / int1 / sin1 / seg40 4 j p13_0 / int2 / sot1 / seg41 5 p p13_1 / int3 / sck1 / seg42 6 j p13_2 / ppg0 / tin0 / frck1 / seg43 7 j p13_3 / ppg1 / tot0 / wot / seg44 8 p p13_4 / sin0 / int6 / seg45 9 h p13_5 / sot0 / adtg / int7 10 m p13_6 / sck0 / ckotx0 11 h p13_7 / ppg2 / ckot0 12 n p04_4 / ppg3 / sda0 13 n p04_5 / ppg4 / scl0 14 i p06_0 / an0 / in2_r / sck5 15 k p06_1 / an1 / in3_r / sot5 16 i p06_2 / an2 / int5 / sin5 17 k p06_3 / an3 / frck0 18 k p06_4 / an4 / in0 / ttg0 / ttg4 19 k p06_5 / an5 / in1 / ttg1 / ttg5 20 k p06_6 / an6 / tin1 / in4_r 21 k p06_7 / an7 / tot1 / in5_r 22 supply avcc 23 g avrh 24 g avrl 25 supply avss 26 k p05_0 / an8 27 k p05_1 / an9 28 k p05_2 / an10 / out2 / sgo1 29 k p05_3 / an11 / out3 / sga1 30 supply vcc 31 supply vss 32 k p05_4 / an12 / int2_r / wot_r 33 k p05_5 / an13 34 k p05_6 / an14 / tin2 / sgo1_r 35 k p05_7 / an15 / tot2 / sga1_r 36 r p08_0 / pwm1p0 / an16 37 r p08_1 / pwm1m0 / an17
document number: 002 - 04715 rev.*a page 11 of 75 mb966a0 series pin no. i/o circuit type * pin name 38 r p08_2 / pwm2p0 / an18 39 r p08_3 / pwm2m0 / an19 40 r p08_4 / pwm1p1 / an20 41 supply dvcc 42 supply dvss 43 r p08_5 / pwm1m1 / an21 44 r p08_6 / pwm2p1 / an22 / ppg6_b 45 r p08_7 / pwm2m1 / an23 / ppg7_b 46 r p09_0 / pwm1p2 / an24 47 r p09_1 / pwm1m2 / an25 48 r p09_2 / pwm2p2 / an26 49 r p09_3 / pwm2m2 / an27 50 t p09_4 / pwm1p3 / ppg12 51 t p09_5 / pwm1m3 / ppg13 52 t p09_6 / pwm2p3 / ppg14 53 supply dvcc 54 supply dvss 55 t p09_7 / pwm2m3 / ppg15 56 s p10_0 / pwm1p4 / sin2 / tin3 / int11 / an28 57 r p10_1 / pwm1m4 / sot2 / tot3 / an29 58 s p10_2 / pwm2p4 / sck2 / ppg6 / an30 59 r p10_3 / pwm2m4 / ppg7 / an31 60 supply vcc 61 supply vss 62 o debug i/f 63 h p17_0 64 c md 65 a x0 66 a x1 67 supply vss 68 b p04_0 / x0a 69 b p04_1 / x1a 70 c rstx 71 j p11_0 / com0 72 j p11_1 / com1 / ppg0_r 73 j p11_2 / com2 / ppg1_r 74 j p11_3 / com3 / ppg2_r 75 j p11_4 / seg0 / ppg3_r 76 j p11_5 / seg1 / ppg4_r
document number: 002 - 04715 rev.*a page 12 of 75 mb966a0 series pin no. i/o circuit type * pin name 77 j p11_6 / seg2 / frck0_r 78 j p11_7 / seg3 / in0_r 79 j p12_0 / seg4 / in1_r 80 h p12_1 / tin1_r / ppg0_b 81 h p12_2 / tot1_r / ppg1_b 82 j p12_3 / seg7 / out2_r 83 j p12_4 / seg8 / out3_r 84 j p12_5 / seg9 / tin2_r / ppg2_b 85 j p12_6 / seg10 / tot2_r / ppg3_b 86 j p12_7 / seg11 / int1_r 87 j p00_0 / seg12 / int3_r 88 j p00_1 / seg13 / int4_r 89 j p00_2 / seg14 / int5_r 90 supply vcc 91 supply vss 92 j p00_3 / seg15 / int6_r 93 j p00_4 / seg16 / int7_r 94 j p00_5 / seg17 / in6 / ttg2 / ttg6 95 j p00_6 / seg18 / in7 / ttg3 / ttg7 96 j p00_7 / seg19 / sgo0 / int14 97 j p01_0 / seg20 / sga0 98 j p01_1 / seg21 / ckot1 / out0 99 j p01_2 / seg22 / ckotx1 / out1 / int15 100 j p01_3 / seg23 / ppg5 101 p p01_4 / seg24 / sin4 / int8 102 j p01_5 / seg25 / sot4 103 p p01_6 / seg26 / sck4 / ttg12 104 j p01_7 / seg27 / ckotx1_r / int9 / ttg13 105 j p02_0 / seg28 / ckot1_r / int10 / ttg14 106 j p02_1 / seg29 / in6_r / ttg15 107 j p02_2 / seg30 / in7_r / ckot0_r / int12 108 j p02_3 / seg31 / sgo0_r / ppg12_b 109 j p02_4 / seg32 / sga0_r / ppg13_b 110 p p02_5 / seg33 / out0_r / int13 / sin5_r 111 j p02_6 / seg34 / out1_r 112 j p02_7 / seg35 / ppg5_r 113 l p03_0 / v0 / seg36 / ppg4_b 114 l p03_1 / v1 / seg37 / ppg5_b 115 l p03_2 / v2 / seg38 / ppg14_b / sot5_r
document number: 002 - 04715 rev.*a page 13 of 75 mb966a0 series *: see i/o circuit type for details on the i/o circuit types. pin no. i/o circuit type * pin name 116 q p03_3 / v3 / seg39 / ppg15_b / sck5_r 117 m p03_4 / rx0 / int4 118 h p03_5 / tx0 119 h p03_6 / int0 / nmi 120 supply vcc
document number: 002 - 04715 rev.*a page 14 of 75 mb966a0 series 6. i/o circuit type type circuit remarks a high - speed oscillation circuit: ? programmable between oscillation mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) ? feedback resistor = approx. 1.0 m ? ? the amplitude : 1.8v 0.15v to operate by the internal supply voltage r fci x out 0 1 x1 x0 f c i or o sc d i sab l e
document number: 002 - 04715 rev.*a page 15 of 75 mb966a0 series type circuit remarks b low - speed oscillation circuit shared with gpio functionality: ? feedback resistor = approx. 5.0 m ? ? gpio functionality selectable (cmos level output (i ol = 4ma, i oh = - 4ma), automotive input with input shutdown function and p rogrammable pull - up resistor) c cmos hysteresis input pin r fci x out 0 1 pout r nout automotive input fci or osc disable standby control for input shutdown standby control for input shutdown automotive input x1a x0a r p-ch p-ch n-ch pull-up control pull-up control pout nout p-ch p-ch n-ch
document number: 002 - 04715 rev.*a page 16 of 75 mb966a0 series type circuit remarks f power supply input protection circuit g ? a/d converter ref+ (avrh) / ref - (avrl) power supply input pin with protection circuit ? without protection circuit against v cc for pins avrh /avrl h ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor i ? cmos level output (i ol = 4ma, i oh = - 4ma) ? cmos hysteresis input with input shutdown function ? programmable pull - up resistor ? analog input p-ch n-ch p-ch n-ch standby control for input shutdown automotive input r pull-up control pout nout p-ch p-ch n-ch standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch analog input hysteresis input
document number: 002 - 04715 rev.*a page 17 of 75 mb966a0 series type circuit remarks j ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor ? seg or com output k ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor ? analog input l ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor ? v n input or seg output standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch seg or co m output automotive input standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch analog input automotive input standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch vn input or s e g output automotive input
document number: 002 - 04715 rev.*a page 18 of 75 mb966a0 series type circuit remarks m ? cmos level output (i ol = 4ma, i oh = - 4ma) ? cmos h ysteresis input with input shutdown function ? programmable pull - up resistor n ? cmos level output (i ol = 3ma, i oh = - 3ma) ? cmos hysteresis input with input shutdown function ? programmable pull - up resistor *: n - channel transistor has slew rate control according to i 2 c spec, irrespective of usage. o ? open - drain i/o ? output 25ma, vcc = 2.7v ? ttl input standby control for input shutdown h y s t e r e s i s in put r pull-up control pout nout p-ch p-ch n-ch standby control for input shutdown h y s t e r e s i s in put r pull-up control pout nout* p-ch p-ch n-ch standby control for input shutdown t t l input r nout n-ch
document number: 002 - 04715 rev.*a page 19 of 75 mb966a0 series type circuit remarks p ? cmos level output (i ol = 4ma, i oh = - 4ma) ? cmos h ysteresis inputs with input shutdown function ? programmable pull - up resistor ? seg or com output q ? cmos level output (i ol = 4ma, i oh = - 4ma) ? cmos hysteresis inputs with input shutdown function ? programmable pull - up resistor ? vn input or seg output r ? cmos level output (programmable i ol = 4ma, i oh = - 4ma and i ol = 30ma, i oh = - 30ma) ? automotive input with input shutdown function ? programmable pull - up / pull - down resistor ? analog input standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch seg or co m output h y s t e r e s i s in put standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch vn inpu t o r seg ou t pu t h y s t e r e s i s in put standby control for input shutdown r pull-up control pull-down control pout nout p-ch p-ch n-ch n-ch analog input automotive input
document number: 002 - 04715 rev.*a page 20 of 75 mb966a0 series type circuit remarks s ? cmos level output (programmable i ol = 4ma, i oh = - 4ma and i ol = 30ma, i oh = - 30ma) ? cmos hysteresis input with input shutdown function ? programmable pull - up / pull - down resistor ? analog input t ? cmos level output (programmable i ol = 4ma, i oh = - 4ma and i ol = 30ma, i oh = - 30ma) ? automotive input with input shutdown function ? programmable pull - up / pull - down resistor standby control for input shutdown r pull-up control pull-down control pout nout p-ch p-ch n-ch n-ch analog input h y s t e r e s i s in put standby control for input shutdown r pull-up control pull-down control pout nout p-ch p-ch n-ch n-ch automotive input
document number: 002 - 04715 rev.*a page 21 of 75 mb966a0 series 7. memory map *1: for details about user rom area, see user rom memory map for flash devices on the following pages. *2: for ramstart addresses, see the table on the next page. *3: unused gpr banks can be used as ram area . gpr: general - purpose register the dma area is only available if the device contains the corresponding resource. the available ram and rom area depends on the device. ff:ffff h de:0000 h dd:ffff h 10:0000 h 0f:c000 h 0e:9000 h 01:0000 h 00:8000 h rams t a r t0* 2 00:0c00 h 00:0380 h 00:0180 h 00:0100 h 00:00f0 h 00:0000 h gpr* 3 dm a reserved peripheral reserved user rom* 1 reserved boot-rom peripheral rom/ram mirror internal ram bank0 peripheral reserved
document number: 002 - 04715 rev.*a page 22 of 75 mb966a0 series 8. ramstart addresses devices bank 0 ram size ramstart0 mb96f6a5 8kb 00:6200 h mb96f6a6 16kb 00:4200 h
document number: 002 - 04715 rev.*a page 23 of 75 mb966a0 series 9. user rom memory map for flash devices *: physical address area of sas - 512b is from df:0000 h to df:01ff h . others (from df:0200 h to df:1fff h ) is m irror area of sas - 512b. sector sas contains the rom configuration block rcba at cpu address df:0000 h - df:01ff h . sas can not be used for e 2 prom emulation. mb96f6a5 mb96f6a6 flash size 128.5kb + 32kb 256.5kb + 32kb cpu mode address flash memory mode address flash size df:a000 h df:9fff h 1f:9fff h df:8000 h 1f:8000 h df:7fff h 1f:7fff h df:6000 h 1f:6000 h df:5fff h 1f:5fff h df:4000 h 1f:4000 h df:3fff h 1f:3fff h df:2000 h 1f:2000 h df:1fff h 1f:1fff h df:0000 h 1f:0000 h de:ffff h de:0000 h sas - 512b* sa2 - 8kb sa1 - 8kb reserved reserved sa4 - 8kb sa3 - 8kb reserved sa2 - 8kb sa1 - 8kb sa4 - 8kb sa3 - 8kb sas - 512b* reserved sa39 - 64kb sa38 - 64kb sa39 - 64kb sa38 - 64kb sa37 - 64kb sa36 - 64kb ff:ffff h 3f:ffff h ff:0000 h 3f:0000 h fe:ffff h 3e:ffff h fe:0000 h 3e:0000 h fd:ffff h 3d:ffff h fd:0000 h 3d:0000 h fc:ffff h 3c:ffff h fc:0000 h 3c:0000 h fb:ffff h bank b of flash a bank a of flash a bank a of flash a
document number: 002 - 04715 rev.*a page 24 of 75 mb966a0 series 10. serial programming communication interface usart pins for flash serial programming (md = 0, debug i/f = 0, serial communication mode) mb96 6a0 pin number usart number normal function 8 usart0 sin0 9 sot0 10 sck0 3 usart1 sin1 4 sot1 5 sck1 56 usart2 sin2 57 sot2 58 sck2 101 usart4 sin4 102 sot4 103 sck4
document number: 002 - 04715 rev.*a page 25 of 75 mb966a0 series 11. interrupt vector table vector number offset in vector table vector name cleared by dma index in icr to program description 0 3fc h callv0 no - callv instruction 1 3f8 h callv1 no - callv instruction 2 3f4 h callv2 no - callv instruction 3 3f0 h callv3 no - callv instruction 4 3ec h callv4 no - callv instruction 5 3e8 h callv5 no - callv instruction 6 3e4 h callv6 no - callv instruction 7 3e0 h callv7 no - callv instruction 8 3dc h reset no - reset vector 9 3d8 h int9 no - int9 instruction 10 3d4 h exception no - undefined instruction execution 11 3d0 h nmi no - non - maskable interrupt 12 3cc h dly no 12 delayed interrupt 13 3c8 h rc_timer no 13 rc clock timer 14 3c4 h mc_timer no 14 main clock timer 15 3c0 h sc_timer no 15 sub clock timer 16 3bc h lvdi no 16 low voltage detector 17 3b8 h extint0 yes 17 external interrupt 0 18 3b4 h extint1 yes 18 external interrupt 1 19 3b0 h extint2 yes 19 external interrupt 2 20 3ac h extint3 yes 20 external interrupt 3 21 3a8 h extint4 yes 21 external interrupt 4 22 3a4 h extint5 yes 22 external interrupt 5 23 3a0 h extint6 yes 23 external interrupt 6 24 39c h extint7 yes 24 external interrupt 7 25 398 h extint8 yes 25 external interrupt 8 26 394 h extint9 yes 26 external interrupt 9 27 390 h extint10 yes 27 external interrupt 10 28 38c h extint11 yes 28 external interrupt 11 29 388 h extint12 yes 29 external interrupt 12 30 384 h extint13 yes 30 external interrupt 13 31 380 h extint14 yes 31 external interrupt 14 32 37c h extint15 yes 32 external interrupt 15 33 378 h can0 no 33 can controller 0 34 374 h - - 34 reserved 35 370 h - - 35 reserved 36 36c h - - 36 reserved 37 368 h - - 37 reserved 38 364 h ppg0 yes 38 programmable pulse generator 0 39 360 h ppg1 yes 39 programmable pulse generator 1
document number: 002 - 04715 rev.*a page 26 of 75 mb966a0 series vector number offset in vector table vector name cleared by dma index in icr to program description 40 35c h ppg2 yes 40 programmable pulse generator 2 41 358 h ppg3 yes 41 programmable pulse generator 3 42 354 h ppg4 yes 42 programmable pulse generator 4 43 350 h ppg5 yes 43 programmable pulse generator 5 44 34c h ppg6 yes 44 programmable pulse generator 6 45 348 h ppg7 yes 45 programmable pulse generator 7 46 344 h - - 46 reserved 47 340 h - - 47 reserved 48 33c h - - 48 reserved 49 338 h - - 49 reserved 50 334 h ppg12 yes 50 programmable pulse generator 12 51 330 h ppg13 yes 51 programmable pulse generator 13 52 32c h ppg14 yes 52 programmable pulse generator 14 53 328 h ppg15 yes 53 programmable pulse generator 15 54 324 h - - 54 reserved 55 320 h - - 55 reserved 56 31c h - - 56 reserved 57 318 h - - 57 reserved 58 314 h rlt0 yes 58 reload timer 0 59 310 h rlt1 yes 59 reload timer 1 60 30c h rlt2 yes 60 reload timer 2 61 308 h rlt3 yes 61 reload timer 3 62 304 h - - 62 reserved 63 300 h - - 63 reserved 64 2fc h rlt6 yes 64 reload timer 6 65 2f8 h icu0 yes 65 input capture unit 0 66 2f4 h icu1 yes 66 input capture unit 1 67 2f0 h icu2 yes 67 input capture unit 2 68 2ec h icu3 yes 68 input capture unit 3 69 2e8 h icu4 yes 69 input capture unit 4 70 2e4 h icu5 yes 70 input capture unit 5 71 2e0 h icu6 yes 71 input capture unit 6 72 2dc h icu7 yes 72 input capture unit 7 73 2d8 h - - 73 reserved 74 2d4 h - - 74 reserved 75 2d0 h - - 75 reserved 76 2cc h - - 76 reserved 77 2c8 h ocu0 yes 77 output compare unit 0
document number: 002 - 04715 rev.*a page 27 of 75 mb966a0 series vector number offset in vector table vector name cleared by dma index in icr to program description 78 2c4 h ocu1 yes 78 output compare unit 1 79 2c0 h ocu2 yes 79 output compare unit 2 80 2bc h ocu3 yes 80 output compare unit 3 81 2b8 h - - 81 reserved 82 2b4 h - - 82 reserved 83 2b0 h - - 83 reserved 84 2ac h - - 84 reserved 85 2a8 h - - 85 reserved 86 2a4 h - - 86 reserved 87 2a0 h - - 87 reserved 88 29c h - - 88 reserved 89 298 h frt0 yes 89 free - running timer 0 90 294 h frt1 yes 90 free - running timer 1 91 290 h - - 91 reserved 92 28c h - - 92 reserved 93 288 h rtc0 no 93 real time clock 94 284 h cal0 no 94 clock calibration unit 95 280 h sg0 no 95 sound generator 0 96 27c h iic0 yes 96 i 2 c interface 0 97 278 h - - 97 reserved 98 274 h adc0 yes 98 a/d converter 0 99 270 h - - 99 reserved 100 26c h - - 100 reserved 101 268 h linr0 yes 101 lin usart 0 rx 102 264 h lint0 yes 102 lin usart 0 tx 103 260 h linr1 yes 103 lin usart 1 rx 104 25c h lint1 yes 104 lin usart 1 tx 105 258 h linr2 yes 105 lin usart 2 rx 106 254 h lint2 yes 106 lin usart 2 tx 107 250 h - - 107 reserved 108 24c h - - 108 reserved 109 248 h linr4 yes 109 lin usart 4 rx 110 244 h lint4 yes 110 lin usart 4 tx 111 240 h linr5 yes 111 lin usart 5 rx 112 23c h lint5 yes 112 lin usart 5 tx 113 238 h - - 113 reserved 114 234 h - - 114 reserved 115 230 h - - 115 reserved
document number: 002 - 04715 rev.*a page 28 of 75 mb966a0 series vector number offset in vector table vector name cleared by dma index in icr to program description 116 22c h - - 116 reserved 117 228 h - - 117 reserved 118 224 h - - 118 reserved 119 220 h - - 119 reserved 120 21c h - - 120 reserved 121 218 h sg1 no 121 sound generator 1 122 214 h - - 122 reserved 123 210 h - - 123 reserved 124 20c h - - 124 reserved 125 208 h - - 125 reserved 126 204 h - - 126 reserved 127 200 h - - 127 reserved 128 1fc h - - 128 reserved 129 1f8 h - - 129 reserved 130 1f4 h - - 130 reserved 131 1f0 h - - 131 reserved 132 1ec h - - 132 reserved 133 1e8 h flasha yes 133 flash memory a interrupt 134 1e4 h - - 134 reserved 135 1e0 h - - 135 reserved 136 1dc h - - 136 reserved 137 1d8 h - - 137 reserved 138 1d4 h - - 138 reserved 139 1d0 h adcrc0 no 139 a/d converter 0 - range comparator 140 1cc h adcpd0 no 140 a/d converter 0 - pulse detection 141 1c8 h - - 141 reserved 142 1c4 h - - 142 reserved 143 1c0 h - - 143 reserved
document number: 002 - 04715 rev.*a page 29 of 75 mb966a0 series 12. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 12.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? recommended operating co nditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operati ng conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applicat ion outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the dev ice. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditio ns if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins sho uld be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large curren t levels in exc ess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, s moke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current f lows do not occur during the power - on sequence. ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are request ed to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from suc h failures by incorporating safety d esign measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions.
document number: 002 - 04715 rev.*a page 30 of 75 mb966a0 series ? precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are de manded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle ope rating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 12.2 precautions for package mounting pac kage mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under cypress 's recommended conditions. for detailed information about mount conditions, contact your sales r epresentative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting onto boards normally involves processes for in serting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for s torage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more e asily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to op en connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. c ypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to cypress mount packages in accordance with cypress ranking of recommended conditions. ? lead - free packaging caution: when b all grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, expo sure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored belo w 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 c /24 h
document number: 002 - 04715 rev.*a page 31 of 75 mb966a0 series ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electricall y ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. 12.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do th e following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage c harges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil ma y lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for enviro nments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to sm oke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 04715 rev.*a page 32 of 75 mb966a0 series 13. handling devices special care is required for the following when handling the device: ? latch - up prevention ? unused pins handling ? external clock usage ? notes on pll clock mode operation ? power supply pins (vcc/vss) ? crystal oscillator and ceramic resonator circuit ? turn on sequence of power supply to a/d converter and analog inputs ? pin handling when not using the a/d converter ? notes on power - on ? stabilization of power supply voltage ? smc power supply pins ? serial communication ? mode pin (md) 1. latch - up prevention cmos ic chips may suffer latch - up under the following conditions: - a voltage higher than v cc or lower than v ss is applied to an input or output pin. - a voltage higher than the rated voltage is applied between vcc pins and vss pins. - the av cc power supply is applied before the v cc voltage. latch - up may increase the power supply current dramatically, causing thermal damages to the device. for the same reason, extra care is required to not let the analog power - supply voltage (av cc , avrh) exceed the digital power - supply voltage. 2 . unused pins handling unused input pins can be left open when the input is disabled (corresponding bit of port input enable register pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damag e of the device. to prevent latch - up, they must therefore be pulled up or pulled down through resistors which should be more than 2k ? . . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull - up/pull - down resistor as described above. 3. external clock usage the permitted frequency range of an external clock depends on the oscillator type and configuration. see ac characteristics for detailed modes and frequenc y limits. single and opposite phase external clocks must be connected as follows: (1) single phase external clock for main oscillator when using a single phase external clock for the main oscillator, x0 pin must be driven and x1 pin left open. and supply 1.8v power to the external clock.
document number: 002 - 04715 rev.*a page 33 of 75 mb966a0 series x0 x1
document number: 002 - 04715 rev.*a page 34 of 75 mb966a0 series (2) single phase external clock for sub oscillator when using a single phase external clock for the sub oscillator, external clock mode must be selected and x0a/p04_0 pin must be driven. x1a/p04_1 pin can be configured as gpio. (3) opposite phase external clock when using an opposite phase external clock, x1 (x1a) pins must be supplied with a clock signal which has the opposite phase to the x0 (x0a) pins. supply level on x0 and x1 pins must be 1.8v. 4. notes on pll clock mode operation if the microcontroller is operated with pll clock mode and no external oscillator is operating or no external clock is suppli ed, the microcontroller attempts to work with the free oscillating pll. performance of this op eration, however, cannot be guaranteed. 5. power supply pins (vcc/vss) it is required that all v cc - level as well as all v ss - level power supply pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly o r be damaged even within the guaranteed operating range. vcc and vss pins must be connected to the device from the power supply with lowest possible impedance. the smoothing capacitor at vcc pin must use the one of a capacity value that is larger than cs. besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 ? ? f between vcc and vss pins as close as possible to vcc and vss pins. 6. crystal oscillator and ceramic resonator circuit noise at x0, x1 pins or x0a, x1a pins might cause abnormal operation. it is required to provide bypass capacitors with shortest possible distance to x0, x1 pins and x0a, x1a pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the u tmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0, x1 pins and x0a, x1a pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu or resonator/mcu system at the quartz or resonator manufacturer, especially when using low - q resonators at higher frequencies. 7. turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/ d converter power supply (av cc , avrh, avrl) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the digital power off after turning the a/d converter supply and analog inputs off. in this case, avrh must not exceed av cc . input voltage for ports shared with analog input ports also must not exceed av cc (turning the analog and digital power supplies simultaneously on or off is acceptable). 8. pin handling when not using the a/d converter if the a/d converter is not used, the power supply pins for a/d converter should be connected such as av cc = v cc , av ss = avrh =avrl = v ss . x0 x1
document number: 002 - 04715 rev.*a page 35 of 75 mb966a0 series 9. notes on power - on to prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50 ? ? s from 0.2v to 2.7v. 10. stabilization of power supply voltage if the power supply voltage varies acutely even within the operation safety range of the v cc power supply voltage, a malfunction may occur. the v cc power s upply voltage must therefore be stabilized. as stabilization guidelines, the power supply voltage must be stabilized in such a way that v cc ripple fluctuations (peak to peak value) in the commercial frequencies (50hz to 60hz) fall within 10% of the standard v cc power supply voltage and the transient fluctuation rate becomes 0.1v/ ? ? s or less in instantaneous fluctuation for power supply switch ing. 11. smc power supply pins all dvcc /dvss pins must be set to the same level as the vcc /vss pins. note that the smc i/o pin state is undefined if dv cc is powered on and v cc is below 3v. to avoid this, v cc must always be powered on before dv cc . dvcc/d vss must be applied when using smc i/o pin as gpio. 12. serial communication there is a possibility to receive wrong data due to noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider re ceiving of wrong data when designing the system. for example apply a checksum and retransmit the data if an error occurs. 13. mode pin (md) connect the mode pin directly to vcc or vss pin. to prevent the device unintentionally entering test mode due to no ise, lay out the printed circuit board so as to minimize the distance from the mode pin to vcc or vss pin and provide a low - impedance connection.
document number: 002 - 04715 rev.*a page 36 of 75 mb966a0 series 14. electrical characteristics 14.1 absolute maximum ratings parameter symbol condition rating unit remarks min max power supply voltage* 1 v cc - v ss - 0.3 v ss + 6.0 v analog power supply voltage* 1 av cc - v ss - 0.3 v ss + 6.0 v v cc = av cc * 2 analog reference voltage * 1 avrh, avrl - v ss - 0.3 v ss + 6.0 v av cc avrh, av cc avrl, avrh > avrl, avrl av ss smc power supply* 1 dv cc - v ss - 0.3 v ss + 6.0 v v cc = av cc = dv cc *2 lcd power supply voltage* 1 v0 to v3 - v ss - 0.3 v ss + 6.0 v v0 to v3 must not exceed v cc input voltage* 1 v i - v ss - 0.3 v ss + 6.0 v v i (d)v cc + 0.3v* 3 output voltage* 1 v o - v ss - 0.3 v ss + 6.0 v v o (d)v cc + 0.3v* 3 maximum clamp current i clamp - - 4.0 +4.0 ma applicable to general purpose i/o pins * 4 total maximum clamp current |i clamp | - - 32 ma applicable to general purpose i/o pins * 4 "l" level maximum output current i ol - - 15 ma normal port i olsmc t a = - 40c - 52 ma high current port t a = +25c - 39 ma t a = +85c - 32 ma t a = +105c - 30 ma "l" level average output current i olav - - 4 ma normal port i olavsmc t a = - 40c - 40 ma high current port t a = +25c - 30 ma t a = +85c - 25 ma t a = +105c - 23 ma "l" level maximum overall output current i ol - - 62 ma normal port i olsmc - - 300 ma high current port "l" level average overall output current i olav - - 31 ma normal port i olavsmc - - 210 ma high current port "h" level maximum output current i oh - - - 15 ma normal port i ohsmc t a = - 40c - - 52 ma high current port t a = +25c - - 39 ma t a = +85c - - 32 ma t a = +105c - - 30 ma "h" level average output current i ohav - - - 4 ma normal port i ohavsmc t a = - 40c - - 40 ma high current port t a = +25c - - 30 ma t a = +85c - - 25 ma t a = +105c - - 23 ma "h" level maximum overall output current i oh - - - 62 ma normal port i ohsmc - - - 300 ma high current port "h" level average overall output current i ohav - - - 31 ma normal port i ohavsmc - - - 210 ma high current port power consumption* 5 p d t a = +105c - 357 *6 mw operating ambient temperature t a - - 40 +105 c storage temperature t stg - - 55 +150 c *1: this parameter is based on v ss = av ss = dv ss = 0v. *2: av cc and v cc and dv cc must be set to the same voltage. it is required that av cc does not exceed v cc , dv cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3: v i and v o should not exceed v cc + 0.3v. v i should also not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. input/output voltages of high current ports depend on dv cc. input/output voltages of standard ports depend on v cc . *4: ? applicable to all general purpose i/o pins (pnn_m). ? use within recommended operating conditions.
document number: 002 - 04715 rev.*a page 37 of 75 mb966a0 series ? use at dc voltage (current). ? the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously o r for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pas s through the protective diode and increase the potential at the v cc pin, and this may affect other device s. ? note that if a +b signal is input when the microcontroller power supply is off (not fixed at 0v), the power supply is prov ided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power - on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power reset. ? the debug i/f pin has only a protective diode against v ss . hence it is only permitted to input a negative clamping current (4ma). for pro tection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6.0v.
document number: 002 - 04715 rev.*a page 38 of 75 mb966a0 series ? sample recommended circuits: *5: the maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: p d = p io + p int p io = (v ol ? i ol + v oh ? i oh ) (i/o load power dissipation, sum is performed on all i/o ports) p int = v cc ? (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the dc characteristics and depends on the selected operation mode and clock frequency and the usage of functions li ke flash programming. i a is the analog current consumption into av cc . *6: worst case value for a package mounted on single layer pcb at specified t a without air flow. warning semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. v cc r +b input (0v to 16v) limiting resistance protective diode p-ch n-ch
document number: 002 - 04715 rev.*a page 39 of 75 mb966a0 series 14.2 recommended operating conditions ( v ss = av ss = dv ss = 0v ) parameter symbol value unit remarks min typ max power supply voltage v cc , av cc , dv cc 2.7 - 5.5 v 2.0 - 5.5 v maintains ram data in stop mode smoothing capacitor at c p in c s 0.5 1.0 to 3.9 4.7 ? f 1.0 ? f (allowance within 50%) 3.9f (allowance within 20%) please use the ceramic capacitor or the capacitor of the frequency response of this level. the smoothing capacitor at v cc must use the one of a capacity value that is larger than c s . warning the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to co ntact their representatives beforehand.
document number: 002 - 04715 rev.*a page 40 of 75 mb966a0 series 14.3 dc characteristics 14.3.1 current r ating (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks min typ max power supply current in run modes *1 i ccpll vcc pll run mode with clks1/2 = clkb = clkp1/2 = 32mhz flash 0 wait (clkrc and clksc stopped) - 28 - ma t a = + 25 c - - 38 ma t a = + 105 c i ccmain main run mode with clks1/2 = clkb = clkp1/2 = 4mhz flash 0 wait (clkpll, clksc and clkrc stopped) - 3.5 - ma t a = + 25 c - - 8 ma t a = + 105 c i ccrch rc run mode with clks1/2 = clkb = clkp1/2 = clkrc = 2mhz flash 0 wait (clkmc, clkpll and clksc stopped) - 1.8 - ma t a = + 25 c - - 6 ma t a = + 105 c i ccrcl rc run mode with clks1/2 = clkb = clkp1/2 = clkrc = 100khz flash 0 wait (clkmc, clkpll and clksc stopped) - 0.16 - ma t a = + 25 c - - 3.5 ma t a = + 105 c i ccsub sub run mode with clks1/2 = clkb = clkp1/2 = 32khz flash 0 wait (clkmc, clkpll and clkrc stopped) - 0.1 - ma t a = + 25 c - - 3.3 ma t a = + 105 c
document number: 002 - 04715 rev.*a page 41 of 75 mb966a0 series parameter symbol pin name conditions value unit remarks min typ max power supply current in sleep modes * 1 i ccspll vcc pll sleep mode with clks1/2 = clkp1/2 = 32mhz (clkrc and clksc stopped) - 9.5 - ma t a = + 25 c - - 15 ma t a = + 105 c i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped) - 1.1 - ma t a = + 25 c - - 4.7 ma t a = + 105 c i ccsrch rc sleep mode with clks1/2 = clkp1/2 = clkrc = 2mhz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped) - 0.6 - ma t a = + 25 c - - 4.1 ma t a = + 105 c i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = clkrc = 100khz (clkmc, clkpll and clksc stopped) - 0.07 - ma t a = + 25 c - - 2.9 ma t a = + 105 c i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz, (clkmc, clkpll and clkrc stopped) - 0.04 - ma t a = + 25 c - - 2.7 ma t a = + 105 c power supply current in timer modes *2 i cctpll pll timer mode with clkp ll = 32mhz (clkrc and clksc stopped) - 1800 2250 ? a t a = + 25 c - - 3220 ? a t a = + 105 c i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped) - 285 330 ? a t a = + 25 c - - 1200 ? a t a = + 105 c i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 (clkpll, clkmc and clksc stopped) - 160 215 ? a t a = + 25 c - - 1110 ? a t a = + 105 c i cctrcl rc timer mode with clkrc = 100khz (clkpll, clkmc and clksc stopped) - 35 75 ? a t a = + 25 c - - 910 ? a t a = + 105 c i cctsub sub timer mode with clksc = 32khz (clkmc, clkpll and clkrc stopped) - 25 65 ? a t a = + 25 c - - 885 ? a t a = + 105 c
document number: 002 - 04715 rev.*a page 42 of 75 mb966a0 series parameter symbol pin name conditions value unit remarks min typ max power supply current in stop mode *3 i cch vcc - - 20 60 ? a t a = + 25 c - - 880 ? a t a = + 105 c flash power down current i cc flashpd - - 36 70 ? a ? power supply current for active low voltage detector* 4 i cclvd low voltage detector enabled - 5 - ? a ? t a = + 25 c - - 12.5 ? a ? t a = + 105 c flash write/ erase current* 5 i ccflash - - 12.5 - ma ? t a = + 25 c - - 20 ma ? t a = + 105 c *1: the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter standby mode and voltage regulator control circuit of t he hardware manual for further details about voltage regulator control. current for "on chip debugger" part is not included. power supply current in run mode does not include flash write / erase current. *2: the power supply current in timer mode is the value when flash is in power - down / reset mode. when flash is not in power - down / reset mode, i ccflashpd must be added to the power supply current. the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz exte rnal clock connected to the sub oscillator. the current for "on chip debugger" part is not included. *3: the power supply current in stop mode is the value when flash is in power - down / reset mode. when flash is not in power - down / reset mode, i ccflashpd m ust be added to the power supply current. *4: when low voltage detector is enabled, i cclvd must be added to power supply current. *5: when flash write / erase program is executed, i ccflash must be added to power supply current.
document number: 002 - 04715 rev.*a page 43 of 75 mb966a0 series 14.3.2 pin c haracteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage v ih port inputs pnn_m - v cc ? 0.7 - v cc + 0.3 v cmos hysteresis input - v cc ? 0.8 - v cc + 0.3 v automotive hysteresis input v ihx0s x0 external clock in " fast clock input mode " v d ? 0.8 - v d v vd=1.8v 0.15v v ihx0as x0a external clock in " oscillation mode " v cc ? 0.8 - v cc + 0.3 v v ihr rstx - v cc ? 0.8 - v cc + 0.3 v cmos hysteresis input v ihm md - v cc - 0.3 - v cc + 0.3 v cmos hysteresis input v ihd debug i/f - 2.0 - v cc + 0.3 v ttl input " l " level input voltage v il port inputs pnn_m - v ss - 0.3 - v cc ? 0.3 v cmos hysteresis input - v ss - 0.3 - v cc ? 0.5 v automotive hysteresis input v ilx0s x0 external clock in " fast clock input mode " v ss - v d ? 0.2 v vd=1.8v 0.15v v ilx0as x0a external clock in " oscillation mode " v ss - 0.3 - v cc ? 0.2 v v ilr rstx - v ss - 0.3 - v cc ? 0.2 v cmos hysteresis input v ilm md - v ss - 0.3 - v ss + 0.3 v cmos hysteresis input v ild debug i/f - v ss - 0.3 - 0.8 v ttl input
document number: 002 - 04715 rev.*a page 44 of 75 mb966a0 series parameter symbol pin name conditions value unit remarks min typ max "h" level output voltage v oh4 4ma type 4.5v (d)v cc 5.5v i oh = - 4ma (d)v cc - 0.5 - (d)v cc v 2.7v (d)v cc < 4.5v i oh = - 1.5ma v oh30 high drive type * 4.5v dv cc 5.5v i oh = - 52ma dv cc - 0.5 - dv cc v t a = - 40 c 2.7v dv cc < 4.5v i oh = - 18ma 4.5v dv cc 5.5v i oh = - 39ma t a = +25 c 2.7v dv cc < 4.5v i oh = - 16ma 4.5v dv cc 5.5v i oh = - 32ma t a = +85 c 2.7v dv cc < 4.5v i oh = - 14.5ma 4.5v dv cc 5.5v i oh = - 30ma t a = +105 c 2.7v dv cc < 4.5v i oh = - 14ma v oh3 3ma type 4.5v v cc 5.5v i oh = - 3ma v cc - 0.5 - v cc v 2.7v v cc < 4.5v i oh = - 1.5ma "l" level output voltage v ol4 4ma type 4.5v (d)v cc 5.5v i ol = +4ma - - 0.4 v 2.7v (d)v cc < 4.5v i ol = +1.7ma v ol30 high drive type * 4.5v dv cc 5.5v i ol = +52ma - - 0.5 v t a = - 40 c 2.7v dv cc < 4.5v i ol = +22ma 4.5v dv cc 5.5v i ol = +39ma t a = +25 c 2.7v dv cc < 4.5v i ol = +18ma 4.5v dv cc 5.5v i ol = +32ma t a = +85 c 2.7v d v cc < 4.5v i ol = +14ma 4.5v d v cc 5.5v i ol = +30ma t a = +105 c 2.7v d v cc < 4.5v i ol = +13.5ma v ol3 3ma type 2.7v v cc < 5.5v i ol = +3ma - - 0.4 v v old debug i/f v cc = 2.7v i ol = +25ma 0 - 0.25 v
document number: 002 - 04715 rev.*a page 45 of 75 mb966a0 series parameter symbol pin name conditions value unit remarks min typ max input leak current i il pnn_m v ss < v i < v cc av ss , avrl < v i < a v cc , avrh - 1 - + 1 ? a single port pin except high current output i/o for smc p08_m , p09_m, p10_m dv ss < v i < d v cc av ss, avrl < v i < a v cc , avrh - 3 - + 3 ? a total lcd leak current |i ilcd | all seg/ com pin v cc = 5.0v - 0.5 10 ? a maximum leakage current of all lcd pins internal lcd divide resistance r lcd between v3 and v2, v2 and v1, v1 and v0 v cc = 5.0v 6.25 12.5 25 k ? pull - up resistance v alue r pu pnn_m v cc = 5.0v 10% 25 50 100 k ? pull - down resistance v alue r down p08_m, p09_m, p10_m v cc = 5.0v 10% 25 50 100 k ? input capacitance c in other than c, vcc, vss, dvcc, dvss, avcc, avss, avrh, avrl, p08_m, p09_m, p10_m - - 5 15 pf p08_m , p09_m, p10_m - - 15 30 pf *: in the case of driving stepping motor directly or high current outputs, set "1" to the bit in the port high drive register (phdrnn:hdx="1").
document number: 002 - 04715 rev.*a page 46 of 75 mb966a0 series 14.4 ac characteristics 14.4.1 main clock input characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, vd=1.8v0.15v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit remarks min typ max input frequency f c x0, x1 4 - 8 mhz when using a crystal oscillator, pll off - - 8 mhz when using an opposite phase external clock, pll off 4 - 8 mhz when using a crystal oscillator or opposite phase external clock, pll on input frequency f fci x0 - - 8 mhz when using a single phase external clock in fast clock input mode, pll off 4 - 8 mhz when using a single phase external clock in fast clock input mode, pll on input clock cycle t cylh - 1 25 - - ns input clock pulse width p wh , p wl - 55 - - ns
document number: 002 - 04715 rev.*a page 47 of 75 mb966a0 series 14.4.2 sub clock input characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks min typ max input frequency f cl x0a, x1a - - 32.768 - khz when using an oscillation circuit - - - 100 khz when using an opposite phase external clock x0a - - - 50 khz when using a single phase external clock input clock cycle t cyll - - 10 - - ? s input clock pulse width - - p wh /t cyll , p wl /t cyll 30 - 70 %
document number: 002 - 04715 rev.*a page 48 of 75 mb966a0 series 14.4.3 built - in rc oscillation characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol value unit remarks min typ max clock frequency f rc 50 100 200 khz when using slow frequency of rc oscillator 1 2 4 mhz when using fast frequency of rc oscillator rc clock stabilization time t rcstab 80 160 320 ? s when using slow frequency of rc oscillator ( 16 rc clock cycles ) 64 128 256 ? s when using fast frequency of rc oscillator (25 6 rc clock cycles ) 14.4.4 internal clock timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol value unit min max internal system clock frequency (clks1 and clks2) f clks1 , f clks2 - 54 mhz internal cpu clock frequency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 - 32 mh z internal peripheral clock frequency (clkp2) f clkp2 - 32 mh z
document number: 002 - 04715 rev.*a page 49 of 75 mb966a0 series 14.4.5 operating conditions of pll (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time t lock 1 - 4 ms for clkmc = 4mhz pll input clock frequency f plli 4 - 8 mhz pll oscillation clock frequency f clkvco 56 - 108 mhz permitted vco output frequency of pll (clkvco) pll phase jitter t pskew - 5 - +5 ns for clkmc (pll input clock) 4mhz 14.4.6 reset input (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit min max reset input time t rstl rstx 10 - ? s rejection of reset input time 1 - ? s rstx 0.2v cc 0.2v cc t rstl
document number: 002 - 04715 rev.*a page 50 of 75 mb966a0 series 14.4.7 power - on reset timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms
document number: 002 - 04715 rev.*a page 51 of 75 mb966a0 series 14.4.8 usart timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c, c l =50pf) parameter symbo l pin name conditions 4.5v ? v cc ?? 5.5v 2.7v ? v cc ? 4.5v uni t min max min max serial clock cycle time t scyc sckn internal shift clock mode 4t clkp1 - 4t clkp1 - ns sck ? ? sot delay time t slovi sck n, sot n - 20 + 20 - 30 + 30 ns sot ? sck ? delay time t ovshi sck n, sot n n ? t clkp1 C 20 * - n ? t clkp1 C 30 * - ns sin ? sck ? setup time t ivshi sck n, sin n t clkp1 + 45 - t clkp1 + 55 - ns sck ? ? sin hold time t shixi sck n, sin n 0 - 0 - ns serial clock " l" pulse width t slsh sck n external shift clock mode t clkp1 + 10 - t clkp1 + 10 - ns serial clock " h" pulse width t shsl sck n t clkp1 + 10 - t clkp1 + 10 - ns sck ? ? sot delay time t slove sck n, sot n - 2t clkp1 + 45 - 2t clkp1 + 55 ns sin ? sck ? setup time t ivshe sck n, sin n t clkp1 /2 + 10 - t clkp1 /2 + 10 - ns sck ? ? sin hold time t shixe sck n, sin n t clkp1 + 10 - t clkp1 + 10 - ns sck fall time t f sck n - 20 - 20 ns sck rise time t r sck n - 20 - 20 ns notes : ? ac characteristic in clk synchronized mode . ? c l is the load capacity value of pins when testing . ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in mb96600 series hardware manual. ? t clkp1 indicates the peripheral clock 1 (clkp1), unit: ns ? these characteristics only guarantee the same relocate port number. for example, the combination of sckn and sotn_r is not guaranteed. *: parameter n depends on t scyc and can be calculated as follows: ? if t scyc = 2 ? k ? ?? t clkp1 , then n = k, where k is an integer > 2 ? if t scyc = (2 ? k + 1) ? t clkp1 , then n = k + 1, where k is an integer > 1 examples: t scyc n 4 ? clkp1 2 5 ? t clkp1 , 6 ? clkp1 3 7 ? clkp1 , 8 ? clkp1 4 ... ...
document number: 002 - 04715 rev.*a page 52 of 75 mb966a0 series t scyc v ol v ol v oh v oh v ih v ih v il v il t slovi t ivshi t shixi v ol sck sot sin internal shift clock mode t ovshi t slsh v ih v ih v ih v ih v il v ih v il v il v il v ol v oh t slove t r t shixe t ivshe t f sck sot sin t shsl external shift clock mode
document number: 002 - 04715 rev.*a page 53 of 75 mb966a0 series 14.4.9 external input timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit remarks min max input pulse width t inh , t inl pnn_m 2 t clkp1 +200 (t clkp1 = 1/f clkp1 )* - ns general purpose i/o adtg a/d converter trigger input tinn, tinn_r reload timer ttgn ppg trigger input frckn, frckn_r free - running timer input clock i nn, inn_r input capture intn, intn_r 200 - ns external interrupt nmi non - maskable interrupt *: t clkp1 indicates the peripheral clock1 (clkp1) cycle time except stop when in stop mode. v ih v il t inl t inh v il external input timing v ih
document number: 002 - 04715 rev.*a page 54 of 75 mb966a0 series 14.4.10 i 2 c timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol conditions typical mode high - speed mode * 4 unit min max min max scl clock frequency f scl c l = 50pf, r = (vp/i ol )* 1 0 100 0 400 khz (repeated) start condition hold time sda ? ? scl ? t hdsta 4.0 - 0.6 - ? s scl clock " l " width t low 4.7 - 1.3 - ? s scl clock " h " width t high 4.0 - 0.6 - ? s (repeated) start condition setup time scl ? ? sda ? t susta 4.7 - 0.6 - ? s data hold time scl ? ? sda ? ? t hddat 0 3.45* 2 0 0.9* 3 ? s data setup time sda ? ? ? scl ? t sudat 250 - 100 - ns stop condition setup time scl ? ? sda ? t susto 4.0 - 0.6 - ? s bus free time between "stop condition" and "start condition" t bus 4.7 - 1.3 - ? s pulse width of spikes which will be suppressed by input noise filter t sp - 0 (1 - 1.5) ?? t clkp1 * 5 0 (1 - 1.5) ?? t clkp1 * 5 ns *1: r and c l represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2: the maximum t hddat only has to be met if the device does not extend the "l" width (t low ) of the scl signal. *3: a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250ns". *4: for use at over 100khz, set the peripheral clock1 (clkp1) to at least 6mhz. *5: t clkp1 indicates the peripheral clock1 (clkp1) cycle time. s da s c l t h d s t a t low t h ddat t s u dat t h i gh t s u s t a t h d s t a t s p t b us t s u s to
document number: 002 - 04715 rev.*a page 55 of 75 mb966a0 series 14.5 a/d converter 14.5.1 electrical c haracteristics for the a/d converter (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit remarks min typ max resolution - - - - 10 bit total error - - - 3.0 - + 3.0 lsb nonlinearity error - - - 2.5 - + 2.5 lsb differential nonlinearity error - - - 1.9 - + 1.9 lsb zero transition voltage v ot ann typ - 20 avrl + 0.5lsb typ + 20 mv full scale transition voltage v fst ann typ - 20 avrh - 1.5lsb typ + 20 mv compare time * - - 1.0 - 5.0 ? s 4.5v v cc 5.5v 2.2 - 8.0 ? s 2.7 v v cc ? 4 .5v sampling time * - - 0.5 - - ? s 4.5v v cc 5.5v 1.2 - - ? s 2.7 v v cc ? 4 .5v power supply current i a av cc - 2.0 3.1 ma a/d converter active i ah - - 3.3 ? a a/d converter not operated reference power supply current (between avrh and avrl) i r avrh - 520 810 ? a ? a/d converter active i rh - - 1.0 ? a ? a/d converter not operated analog input capacity c vin an0 to 15 - - 16.0 pf normal outputs an16 to 31 - - 17.8 pf high current outputs analog impedance r vin ann - - 2050 ? 4.5v av cc 5.5v - - 3600 ? 2.7v av cc < 4.5v analog port input current (during conversion) i ain an0 to 15 - 0.3 - + 0.3 ? a av ss , avrl ?? v ain ? av cc , avrh an16 to 31 - 3.0 - + 3.0 ? a analog input voltage v ain ann avrl - avrh v reference voltage range - avrh av cc - 0.1 - av cc v - avrl av ss - av ss + 0.1 v variation between channels - ann - - 4.0 lsb *: time for each channel.
document number: 002 - 04715 rev.*a page 56 of 75 mb966a0 series 14.5.2 accuracy and s etting of the a/d converter s ampling t ime if the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the a/d conversion precision. to satisfy the a/d conversion precision, a sufficient sampling time must be selected. the required sampling time (tsamp) depends on the external dr iving impedance r ext , the board capacitance of the a/d converter input pin c ext and the av cc voltage level. the following replacement model can be used for the calculation: r ext : external driving impedance c ext : capacitance of pcb at a/d converter input c vin : analog input capacity (i/o, analog switch and adc are contained) r vin : analog input impedance (i/o, analog switch and adc are contained) the following approximation formula for the replacement model above can be used: tsamp = 7.62 ? ( rext ? cext + ( rext + r vin ) ? c vin ) ? do not select a sampling time below the absolute minimum permitted value . (0.5 ? s for 4.5v av cc 5.5v , 1.2 ? s for 2.7 v av cc < 4.5v) ? if the sampling time cannot be sufficient, connect a capacitor of about 0.1 ? f to the analog input pin. ? a big external driving impedance also adversely affects the a/d conversion precision due to the pin input leakage current iil (static current before the sampling switch) or the analog input leakage current iain (total leakage current of pin inpu t and comparator during sampling). the effect of the pin input leakage current iil cannot be compensated by an external capacitor. ? the accuracy gets worse as |avrh - avrl | becomes smaller. sampling switch (d u r i n g s a m p l i n g : o n) c vin r vin analog i n put mcu r ext c ext source c o m p a r a t o r
document number: 002 - 04715 rev.*a page 57 of 75 mb966a0 series 14.5.3 definition of a/d converter terms resolution : analog variation that is recognized by an a/d converter. nonlinearity error : deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 0b0000000001) to the full - scale transition point (0b1111111110 0b1111111111). differential nonlinearity error : deviation from the ideal value of the input voltage that is required to change the output c ode by 1lsb. total error : difference between the actual value and the theoretical value. the total error includes z ero transition error, full - scale transition error and nonlinearity error. zero transition voltage: input voltage which results in the minimum conversion value. full scale transition voltage: input voltage which results in the maximum conversion value. nonl inearity error of digital output n = v nt - {1lsb ? (n - 1) + v ot } [lsb] 1lsb differential non linearity error of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v ot 1022 n : a/d converter digital output value. v ot : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0x3fe to 0x3ff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn.
document number: 002 - 04715 rev.*a page 58 of 75 mb966a0 series 1lsb (ideal value) = avrh - avrl [v] 1024 total error of digital output n = v nt - {1lsb ? (n - 1) + 0.5lsb} 1lsb n : a/d converter digital output value. v nt : voltage at which the digital output changes from 0x(n + 1) to 0xn. v ot (ideal value) = avrl + 0.5lsb[v] v fst (ideal value) = avrh - 1.5lsb[v]
document number: 002 - 04715 rev.*a page 59 of 75 mb966a0 series 14.6 high c urrent o utput s lew r ate (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditi o ns value unit remarks min typ max output rise/fall time t r30 , t f30 p08_m, p09_m, p10_m outputs driving strength set to "30ma" 15 - 75 ns c l =85pf v h v h voltage time v l v l v h =v ol30 +0.9 (v oh30 -v ol30 ) v l =v ol30 +0.1 (v oh30 -v ol30 ) t r30 t f30
document number: 002 - 04715 rev.*a page 60 of 75 mb966a0 series 14.7 low v oltage d etection function c haracteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol conditions value unit min typ max detected voltage *1 v dl0 cilcr:lvl = 0000 b 2.70 2.90 3.10 v v dl1 cilcr:lvl = 0001 b 2.79 3.00 3.21 v v dl2 cilcr:lvl = 0010 b 2.98 3.20 3.42 v v dl3 cilcr:lvl = 0011 b 3.26 3.50 3.74 v v dl4 cilcr:lvl = 0100 b 3.45 3.70 3.95 v v dl5 cilcr:lvl = 0111 b 3.73 4.00 4.27 v v dl6 cilcr:lvl = 1001 b 3.91 4.20 4.49 v power supply voltage change rate *2 dv/dt - - 0.004 - + 0.004 v/ ? s hysteresis width v hys cilcr:lvhys=0 - - 50 mv cilcr:lvhys=1 80 100 120 mv stabilization time t lvdstab - - - 75 ? s detection delay time t d - - - 30 ? s ? d ), there is a possibility that the low voltage detection will occur or stop after the power supply voltage passes the detection range. *2: in order to perform the low voltage detection at the detection voltage (v dlx ), be sure to suppress fluctuation of the power supply voltage within the limits of the change ration of power supply voltage.
document number: 002 - 04715 rev.*a page 61 of 75 mb966a0 series t i m e v c c v dlx m i n v o l t a g e v dlx m a x d v d t d e t e c t e d v o l t a g e rcr: l v de lo w v o l t age detection function enab l e low voltage detection function disable s t ab ili z a t i on t i m e t l v d s t a b lo w v o l t age detection function enab l e
document number: 002 - 04715 rev.*a page 62 of 75 mb966a0 series 14.8 flash memory write/erase characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter conditions value unit remarks min typ max sector erase time large sector - - 1.6 7.5 s includes write time prior to internal erase. small sector - - 0.4 2.1 s security sector - - 0.31 1.65 s w ord (16 - bit) write time - - 25 400 ? s not including system - level overhead time. chip erase time - - 8.31 40.05 s includes write time prior to internal erase . note: while the flash memory is written or erased, shutdown of the external power (v cc ) is prohibited. in the application system where the external power (v cc ) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function. to put it concrete, change the external power in the range of change ration of power supply voltage ( - 0.004v/ ? ? s to +0.004v/ ? ? s) after the external power falls below the detection voltage (v dlx ) *1 . write/erase cycles and data hold time write / erase cycles (cycle) data hold time (year) 1,000 20 *2 10,000 10 *2 100,000 5 *2 *1: see " 14. 7. low voltage detection function characteristics". *2: this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 ? c ).
document number: 002 - 04715 rev.*a page 63 of 75 mb966a0 series 15. example characteristics this characteristic is an actual value of the arbitrary sample. it is not the guaranteed value. ? mb96f6 a6 0 . 0 1 0 . 1 0 1 . 0 0 1 0 . 0 0 1 0 0 . 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] r un m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v ) rc c l o c k ( 2 m h z ) 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 1 0 . 0 0 0 1 0 0 . 0 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] s l eep m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v )
document number: 002 - 04715 rev.*a page 64 of 75 mb966a0 series ? mb96f6 a6 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 1 0 . 0 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] t i m e r m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v cc = 5 . 5 v ) 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] s t op m od e ( v c c = 5 . 5 v )
document number: 002 - 04715 rev.*a page 65 of 75 mb966a0 series ? used setting mode selected source clock clock/regulator and flash settings run mode pll clks1 = clks2 = clkb = clkp1 = clkp2 = 32mhz main osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 4mhz rc clock fast clks1 = clks2 = clkb = clkp1 = clkp2 = 2mhz rc clock slow clks1 = clks2 = clkb = clkp1 = clkp2 = 100khz sub osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 32khz sleep mode pll clks1 = clks2 = clkp1 = clkp2 = 32mhz regulator in high power mode, (clkb is stopped in this mode) main osc. clks1 = clks2 = clkp1 = clkp2 = 4mhz regulator in high power mode, (clkb is stopped in this mode) rc clock fast clks1 = clks2 = clkp1 = clkp2 = 2mhz regulator in high power mode, (clkb is stopped in this mode) rc clock slow clks1 = clks2 = clkp1 = clkp2 = 100khz regulator in low power mode, (clkb is stopped in this mode) sub osc. clks1 = clks2 = clkp1 = clkp2 = 32khz regulator in low power mode, (clkb is stopped in this mode) timer mode pll clkmc = 4mhz, clkpll = 32mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode main osc. clkmc = 4mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode rc clock fast clkmc = 2mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode rc clock slow clkmc = 100khz (system clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode sub osc. clkmc = 32 khz (system clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode stop mode stopped (all clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode
document number: 002 - 04715 rev.*a page 66 of 75 mb966a0 series 16. ordering inform a tion mcu with can controller part number flash memory package * mb96f6 a5 rbpmc - gse1 flash a ( 160 .5kb) 120 - pin plastic lqfp (fpt - 120 p - m 21 ) mb96f6 a5 rbpmc - gse2 mb96f6 a6 rbpmc - gse1 flash a ( 288 .5kb) 120 - pin plastic lqfp (fpt - 120 p - m2 1 ) mb96f6 a6 rbpmc - gse2 *: for details about package, see " package dimension ". mcu without can controller part number flash memory package * mb96f6 a5 a b pmc - gs e1 flash a (160.5kb) 120 - pin plastic lqfp (fpt - 120 p - m 21 ) mb96f6 a5 a b pmc - gs e2 *: for details about package, see " package dimension ".
document number: 002 - 04715 rev.*a page 67 of 75 mb966a0 series 17. package dimension 120-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 16.0 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.88 g code (reference ) p-lfqfp120-16 16-0.5 0 120-pin plastic lqfp (fpt -120p-m21) (fpt-120p-m21) c 2002-2010 fujitsu semiconductor limited f120033s-c-4-7 1 30 60 31 90 61 120 91 sq 18.000.20(.709.008)sq 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) index .006 C.001 +.002 C0.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 C.004 +.008 C0.10 +0.20 1.50 details of "a" part (mounting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0~8 * .630 C.004 +.016 C0.10 +0.40 16.00 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. resin protrusion is +0.25(.010) max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002 - 04715 rev.*a page 68 of 75 mb966a0 series 18. major changes spansion publication number: mb96f6a6 - ds704 - 00010 page section change results revision 1.0 - - preliminary data sheet 2 features changed the description of system clock up to 16 mhz external clock for devices with fast clock input feature up to 8 mhz external clock for devices with fast clock input feature 3 changed the description of f ree - running timers signals an interrupt on overflow signals an interrupt on overflow , supports timer clear upon match with output compare (0, 4) 4 changed the description of lcd controller on - chip drivers for internal divider resistors or external divider resistors i nternal divider resistors or external divider resistors changed the description of external interrupts interrupt mask and pending bit per channel interrupt mask bit per channel 5 changed the description of built - in on chip debugger - event sequencer: 2 levels - event sequencer: 2 levels + reset 6 product lineup added the product changed the remark of rlt rlt 0/1/2/3/6 only rlt6 can be used as ppg clock source rlt 0 to 3/6 changed number of the i/o ports 96 (dual clock mode) 98 (single clock mode) 95 (dual clock mode) 97 (single clock mode) 7 block diagram deleted the block of rlt6 from ppg block changed the rlt block 4 ch 0/ 1/2/ 3/ 6 5 ch 9 pin description changed the description of ppg n_b programmable pulse generator n output (8bit) programmable pulse generator n output (16bit/8bit) 13 pin circuit type changed the i/o circuit type of pin no.116 p q 15 i/o circuit type changed the figure of type b changed the remarks of type b (cmos hysteresis input with input shutdown function, i ol = 4ma, i oh = - 4ma, programmable pull - up resister) ( cmos level output (i ol = 4ma, i oh = - 4ma), automotive input with input shutdown function and programmable pull - up resistor) 16 changed the figure of type g 19 added the type q 21 memory map changed the start addresses of boot - rom 0f:e000 h 0f:c000 h
document number: 002 - 04715 rev.*a page 69 of 75 mb966a0 series page section change results 23 user rom memory map for flash devices changed the annotation others (from df:0200 h to df:1fff h ) are all mirror area of sas - 512b. others (from df:0200 h to df:1fff h ) is mirror area of sas - 512b. 25 interrupt vector table changed the description of call v0 to call v7 reserved callv inst ruction changed the description of reset reserved reset vector changed the description of int9 reserved int9 instruction changed the description of exception reserved undefined instruction execution 26 changed the vector name of vector number 64 ppgrlt rlt6 changed the description of vector number 64 reload timer 6 can be used as ppg clock source reload timer 6 29 to 32 handling precautions ? added a section 34 handling devices added the description to 3. external clock usage (3) opposite phase external clock changed the description in 7. turn on sequence of power supply to a/d converter and analog inputs in this case, the voltage must not exceed avrh or av cc in this case, avrh must not exceed av cc . input voltage for ports shared with analog input ports also must not exceed av cc 35 handling devices ? changed the description in 1 1 . smc power supply pins to avoid this, v cc must always be powered on before dv cc . to avoid this, v cc must always be powered on before dv cc . dv cc /dv ss must be applied when using smc i/o pin as gpio. added the description 13. mode pin (md) 36 electrical characteristics absolute maximum ratings changed the symbol of "l" level average overall output current i olsmcav i olavsmc changed the symbol of " h " level average overall output current i ohsmcav i ohavsmc 37 changed the annotation *2 it is required that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. it is required that av cc does not exceed v cc , dv cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. changed the annotation *3 input/output voltages of standard ports depend on v cc . input/output voltages of high current ports depend on dv cc . input/output voltages of standard ports depend on v cc .
document number: 002 - 04715 rev.*a page 70 of 75 mb966a0 series page section change results changed the annotation *4 note that if the +b input is applied during power - on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power reset (except devices with persistent low voltage reset in internal vector mode). note that if the +b input is applied during power - on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power reset. added the annotation *4 the debug i/f pin has only a protective diode against v ss . hence it is only permitted to input a negative clamping current (4ma). for protection against positive input vo ltages, use an external clamping diode which limits the input voltage to maximum 6.0v. 39 recommended operating conditions added the value and remarks to power supply voltage min: 2.0v typ: - max: 5.5v remarks: maintains ram data in stop mode changed the value of smoothing capacitor at c p in typ: 1.0 ? f 1.0 ? f to 3.9 ? f max: 1.5 ? f 4.7 ? f changed the remarks of smoothing capacitor at c p in deleted (target value) added 3.9 ? f (allowance within 20%) 40 dc characteristics current rating deleted (target value) added the symbol to power supply current in run modes i ccrch , i ccrcl changed the conditions of i ccpll , i ccmain , i ccsub in power supply current in run modes flash 0 wait is added changed the value of power supply current in run modes i ccpll typ: 28.5ma 28ma (t a = +25c) i ccmain typ:5 ma 3.5 ma (t a = +25c) max: 10 ma 8 ma (t a = +105c) i ccsub typ:0.5 ma 0.1 ma (t a = +25c) max: 6ma 3.3 ma (t a = +105c) 41 added the symbol to power supply current in sleep modes i ccsrch , i ccsrcl changed the conditions of i ccsmain in power supply current in sleep modes smcr:lpmss=0 is added changed the value of power supply current in sleep modes i ccspll typ:10 ma 9.5 m a (t a = +25c) i ccsmain typ: 3 ma 1.1 m a (t a = +25c) max: 8 ma 4 .7 m a (t a = +105c) i ccssub typ: 0. 3 ma 0.04m a (t a = +25c) max: 4 .5 ma 2. 7 m a (t a = +105c) added the symbol to power supply current in timer modes i cctpll changed the conditions of i cctmain , i cctrch in power supply current in timer modes smcr:lpmss=0 is added
document number: 002 - 04715 rev.*a page 71 of 75 mb966a0 series page section change results 41 dc characteristics current rating changed the value of power supply current in timer modes i cc t main max : 355 ? a 330 ? a (t a = +25c) max: 1320 ? a 1200 ? a (t a = +105c) i cc trch max : 245 ? a 215 ? a (t a = +25c) max: 1230 ? a 1110 ? a (t a = +105c) i cc trcl max : 105 ? a 75 ? a (t a = +25c) max: 1030 ? a 910 ? a (t a = +105c) i cc t sub typ: 90 ? a 65 ? a (t a = +25c) max: 1000 ? a 885 ? a (t a = +105c) 42 changed the value of power supply current in stop modes i cch max: 90 ? a 60 ? a (t a = +25c) max: 1000 ? a 880 ? a (t a = +105c) added the symbol i ccflashpd changed the value and condition of power supply current for active low voltage detector i cclvd typ: 5 ? a, max: 15 ? a, remarks: nothing typ: 5 ? a, max: - , remarks: t a = +25c typ: - , max: 12.5 ? a, remarks: t a = +105c changed the condition of flash write/erase current i ccflash typ: 12.5 ma , max : 20 ma, remarks : nothing typ: 12.5 ma , max : - , remarks : t a = + 25c typ: - , max : 20ma, remarks : t a = +10 5c changed the annotation *2 the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz exter nal clock connected to the sub oscillator. the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz exter nal clock connected to the sub oscillator. the current for "on chip debugger" part is not included. 44 dc characteristics pin characteristics added the symbol for debug i/f pin v old
document number: 002 - 04715 rev.*a page 72 of 75 mb966a0 series page section change results 45 dc characteristics pin characteristics changed the pin name of input capacitance other than vcc, vss, avcc, avss, avrh, avrl, p08_m , p09_m, p10_m other than c, vcc, vss, dvcc , dvss, avcc, avss, avrh, avrl, p08_m , p09_m, p10_m deleted the annotation i oh and i o l are target value. added the annotation in the case of driving stepping motor directly or high current outputs, set "1" to the bit in the port high drive register (phdrnn:hdx="1"). 46 ac characteristics main clock input characteristics changed max frequency for f fci in all conditions 16 8 changed min frequency for t cylh 62.5 125 changed min, max and unit for p wh , p wl min: 30 55 max: 70 - unit: % ns added the f igure (t cylh ) when using the external clock 47 ac characteristics sub clock input characteristics added the f igure (t cyll ) when using the crystal oscillator clock 48 ac characteristics built - in rc oscillation characteristics added rc clock stabilization time 49 ac characteristics operating conditions of pll changed the value of pll input clock frequency max: 16mhz 8mhz changed the symbol of pll oscillation clock frequency f pllo f clkvco added remarks to pll oscillation clock frequency added pll phase jitter and the figure ac characteristics reset input added the figure for reset input time (t rstl ) 51 ac characteristics usart timing changed the condition (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c, c l = 50pf) changed the hardware manual mb966 a 0 series hardware manual mb96600 series hardware manual 52 c hanged the figure for internal shift clock mode 54 ac characteristics i 2 c timing ? added parameter, noise filter and an annotation *5 for it added t sp to the figure ?
document number: 002 - 04715 rev.*a page 73 of 75 mb966a0 series page section change results 55 a/d converter electrical characteristics for the a/d converter added analog impedance added variation between channels added the annotation 56 a/d converter accuracy and setting of the a/d converter sampling time deleted the unit [min] from approximation formula of sampling time 57 a/d converter definition of a/d converter terms changed the description and the figure linearity nonlinearity differential linearity error differential nonlinearity error changed the description linearity error: deviation of the line between the zero - transition point (0b00000000000b0000000001) and the full - scale transition point (0b11111111100b1111111111) from the actual conversion characteristics. nonlinearity error: deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 0b0000000001) to the full - scale transition point (0b1111111110 0b1111111111). added the description zero transition voltage full scale transition voltage 59 high current output slew rate changed the symbol and figure t r2 , t f2 , v ol2 t r30 , t f30 , v ol30 60 low v oltage d etection function c haracteristics added the value of power supply voltage change rate max: +0.004 v/ ? s added hysteresis width ( v hys ) added stabilization time ( t lvdstab ) added detection delay time ( t d ) deleted the remarks added the annotation *1 , *2 61 added the figure for h ysteresis width added the figure for stabilization time 62 flash memory write/erase characteristics changed the value of sector erase time added security sector to sector erase time changed the parameter half word (16 bit) write time w ord (16 - bit) write time changed the value of chip erase time changed the remarks o f sector erase time excludes write time prior to internal erase includes write time prior to internal erase added the note and annotation *1 deleted (targeted value) from title write/erase cycles and data hold time 63 to 65 example characteristics added a section 66 ordering i nformation ? changed part number mcu with can controller mb96f6 a 6rapmc - gse1* mb96f6 a 6rbpmc - gse1 mb96f6 a 6rapmc - gse2* mb96f6 a 6rbpmc - gse 2
document number: 002 - 04715 rev.*a page 74 of 75 mb966a0 series page section change results added part number mcu with can controller mb96f6 a 5rbpmc - gse1 mb96f6 a 5rbpmc - gse2 mcu without can controller mb96f6 a 5abpmc - gse1 mb96f6 a 5abpmc - gse2 revision 1.1 - - company name and layout design change note: please see document history about later revised information. document history document title: mb96f6a5r/a, mb96f6a6r, f2mc - 16fx mb966a0 series 16 - bit proprietary microcontroller data sheet document number: 00 2 - 0 4715 revision ecn orig. of change submission date description of change ** ? tors 01/31 /201 4 migrated to cypress and assig ned document number 002 - 4715 . no change to document contents or format. * a 5166254 tors 0 5 / 2 5 /2016 updated to cypress template
document number: 002 - 04715 rev.*a may 25, 2016 page 75 of 75 mb966a0 series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to y ou, visit us at cypress locations . products arm? cortex? microcontrollers cypress.com/arm automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress.com/go/interface lighting & power control cypress.com/go/powerpso c memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support ? cypress semiconductor corporation 2011 - 2016. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc ("cypre ss"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellectual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this para graph, grant any license under its paten ts, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you u nder its copyright rights in the software, a personal, non - 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